Sampling circuits are known from the state of the art. A sampling circuit can be employed for example in a receiver for sampling received signals.
A conventional receiver is usually implemented with complicated analog techniques and using BiCMOS (bipolar complementary metal-oxide semiconductor) or other analog-oriented semiconductor.
For illustration, a block diagram of an exemplary analog direct conversion receiver is presented as FIG. 1.
The depicted receiver comprises a low noise amplifier (LNA) 10 for amplifying received radio frequency (RF) signals, mixers 11 for downconverting the amplified RF signals, an analog signal processing component 12 for processing the downconverted signals, analog-to-digital converters (ADC) 13 for converting the processed analog signals into digital signals, and a digital signal processing component (DSP) 14 for further processing of the digital signals. For processing the analog downconverted signal, the analog signal processing component 12 comprises an Nth-order low-pass filter (LPF), an analog gain control (AGC), a direct-current (DC) offset cancellation, etc. For processing the digital signal, the DSP 14 comprises a decimation stage, an LPF, etc. The output of the DSP 22 constitutes the digital baseband (BB) output.
This kind of receiver requires high-order analog base band filters to attenuate undesired signals, and at the same time, it has a high in-band amplification. Depending on the involved system, e.g., GSM (global system for mobile communications), CDMA (code division multiple access), WCDMA (wideband CDMA), etc., up to seventh-order analog filters may be required. In addition to the complicated filter, also an accurate AGC is needed in order to relax ADC requirements in terms of sampling frequency, dynamic range and related silicon costs. To this end, a large number of high quality resistors and capacitors is needed in the implementation. Due to large temperature dependency and process variations of the resistor-capacitor (RC) time constants, often some kind of calibration or tuning is required in addition. Moreover, high quality resistors require additional mask layers, which also increase the costs of the production process.
Due to cost reasons, it is therefore often desirable to increase the integration level by digitalization, that is, to implement RF receivers and analog input interface circuits in a pure digital semiconductor process, for example in a deep sub-micron CMOS, together with the digital signal processing blocks. Also to support this trend, circuit techniques are being developed that enable signal processing functions, which are conventionally implemented in the analog domain, like filtering, to be implemented with digital techniques.
A block diagram of a more digital implementation of a direct conversion receiver is presented as FIG. 2.
The receiver of FIG. 2 comprises again an LNA 20 for amplifying received RF signals. Further, it comprises a first integrated processing component 21 for processing the received analog signals. This processing includes a frequency down conversion, an analog pre-filtering and an analog-to-digital conversion by ADCs. The receiver comprises in addition a DSP 22 for processing the resulting digital signals. The DSP 22 realizes more specifically a decimation, a low-pass filtering, an automatic gain control, a direct-current (DC) offset cancellation, etc. The output of the DSP 22 constitutes the digital baseband (BB) output.
The benefits of the digitalization of the RF and analog interface circuits include an increased integration level, a size reduction with time through process technology shrinkage, an increased flexibility and adaptability of the circuits, shorter design cycles which are made possible through design synthesis, portability and reuse of the circuits, an ease of the implementation of the complex signal processing in the digital domain, less calibration in the production, and a better control of performance.
One approach for realizing a digitalization of an RF receiver is utilizing a subsampling technique, where the frequency downconversion and the sampling are combined and performed by a voltage mode sampling operation. This solution, however, has the drawback that it still needs a continuous time antialias filter. Actually, a voltage mode sampling operation makes the antialias filter implementation even more complicated compared to the conventional direct conversion RF receiver, because it requires a very selective bandpass filter at the RF frequencies.
A more promising approach for realizing a digitalization of an RF receiver by a system-on-chip (SoC) solution is utilizing a current mode sampling operation, which is also called charge sampling. The current mode sampling has several advantages over the voltage mode sampling. A current mode sampling operation contains an inherent antialias filtering. Therefore the additional antialias filter needed in conventional voltage mode sampling can be avoided. The antialias filter frequency response does not have to be calibrated, because it is proportional to the capacitor ratio and the clock frequency, which are among the best-controlled parameters in the analog semiconductor integration. A current mode sampling operation is moreover suitable for an implementation with a pure digital deep-submicron CMOS process, because additional mask layers needed for high quality resistors can be avoided. Further, the frequency down-conversion can be combined easily with the current mode sampling circuit.
The operational principle of a current mode sampling without frequency down-conversion is illustrated by the schematic circuit of FIG. 3. The circuit comprises a transconductance element (GM) 30, which is connected via a first switching element S31 and a second switching element S32 to an output. Between the first switching element S31 and the second switching element S32, a sampling capacitor C30 and a third switching element 33 are connected in parallel to each other to ground.
The transconductance element 30 converts an input voltage mode signal VIN into a current mode signal. The first switching element S31 is closed during an integration period φ1, and the current mode signal is integrated by the sampling capacitor C30 during this integration period φ1. After the integration period φ1, the resulting voltage across capacitor C30 is then sampled by the subsequent stages for further processing. The resulting voltage VOUT is provided to subsequent stages more specifically by closing the second switching element S32 during a discharging period φ2. Before the next integration period φ1 is entered for a new sample, the sampling capacitor C30 is reset by closing the third switching element S33.
FIG. 4 presents a current mode sampling circuit with frequency down-conversion, in which a transconductance element 40, switching elements S41, S42 and S43 and a sampling capacitance C40 are arranged in the same manner as in FIG. 3. In the circuit of FIG. 4, however, a switching element S44, which performs the frequency down-conversion, is inserted between the transconductance element 40 and the actual sampling circuit with elements C40, S41, S42 and S43. The switching element S44 is controlled by a local oscillator signal LO.
The transconductance element 40 converts an input RF voltage mode signal VRF into a current mode signal. The resulting current mode signal is then frequency down-converted by the switching element S44. The purpose of the down-conversion is to bring the current signal provided by the transconductance element 40 from the radio frequency down to a frequency range in which it can be sampled with sufficient performance, e.g. to an intermediate frequency (IF) or to the base band (BB), as indicated in the diagram of FIG. 5. The subsequent sampling is the same as in the circuit of FIG. 3. That is, switching element S41 is closed during integration periods φ1 such that the current mode signal is integrated by the sampling capacitor C40. The resulting BB or IF voltage VBB/VIF across capacitor C40 is provided to subsequent stages by closing the second switching element S42 during discharging periods φ2. Before the next integration period φ1, the sampling capacitor C40 is reset by closing the third switching element S43.
Such a current mode sampling has been presented for example by Jiren Yuan in: “A Charge Sampling Mixer With Embedded Filter Function for Wireless Applications”, 2nd International Conference on Microwave and Millimeter Wave Technology Proceedings, 2000, by Karvonen S. in: “Analysis and Realization of a Downconverting Quadrature Sampler”, Diploma Thesis, University of Oulu, 2001, by Karvonen S., Riley T. and Kostamovaara J. in: “A Low Noise Quadrature Subsampling Mixer”, IEEE International Symposium on Circuits and Systems 2001, Volume 4, and by Karvonen S., Riley T. and Kostamovaara J. in: “Charge Sampling Mixer With DS Quantized Impulse Response”, IEEE International Symposium on Circuits and Systems 2002, volume 1.
The integration of a current mode signal over a given period of time produces a SINC=sin(x)/x type of frequency domain transfer function, which has transmission zeros at the sampling frequency Fs and its multiples 2Fs, 3Fs, etc. Thus, the transfer function zeros create an inherent anti-alias filter for the sampling operation. That is, folding interferences and noise are filtered due to the inherent antialias filtering. The transfer function and the aliasing of the current mode sampling are sketched in FIG. 6. As can be seen, the transfer function has a significant attenuation of the aliasing frequency bands, i.e. around the zeros at Fs, 2Fs, 3Fs, etc., especially near the sampling frequency Fs. Therefore, a current mode sampling is well suited for use with over-sampling ADCs, in which the signal band is narrow compared to the sampling frequency.
On the whole, it is to be understood that the current mode sampling does not constitute a kind of sub-sampling, and thus, it does not have the problems associated with, for example, voltage mode RF sub-sampling.
FIG. 7 presents a straightforward implementation of the passive current mode sampling with frequency down conversion as shown in FIG. 4. In FIG. 7, the passive current mode sampling and the frequency down conversion are further combined with a switched-capacitor integrator for low-pass filtering.
The circuit of FIG. 7 thus comprises a transconductance element 70, a frequency down-conversion portion 71, a sampling portion 72 and an LPF portion 75.
The transconductance element 70 has two inputs and two outputs, the latter being connected to the frequency down-conversion portion 71. The frequency down-conversion portion 71 comprises four switches which are controlled by a local oscillator.
In the sampling portion 72, a first path is realized, which connects a first output of the frequency down-conversion portion 71 via a switch S71a, a sampling capacitor Csa and a switch S72a to a first output of the sampling portion 72. In this first path, the first output of the frequency down-conversion portion 71 is further connected via a capacitor Cia to ground Vcm. In addition, the connection between switch S71a and capacitor Csa is connected via a switch S73a to ground Vcm, while the connection between capacitor Csa and switch S72a is connected via a switch S74a to ground Vcm. The second output of the frequency down-conversion portion 71 is connected in exactly the same manner via a second path realized in the sampling portion 72 to a second output of the sampling portion 72. In the second path, corresponding capacitors are named Csb and Cib instead of Csa and Cia, respectively, and corresponding switches are named S71b to S74b instead of S71a to S74a, respectively.
The capacitors Csa and Csb and the switches S71a to S74a and S71b to S74b of the first and the second path form a first sampler 73. Additionally, identical samplers 74 etc. may be connected in parallel to the first sampler 73.
The LPF portion 75 comprises an operational amplifier 76.
The first output of the sampling portion 72 is connected via a first input of the LPF portion 75 to a first input of operational amplifier 76, and a first output of operational amplifier 76 is connected to a first output of the LPF portion 75. A capacitor C1a on the one hand and a series connection of a switch S75a, a capacitor C2a and a switch S76a on the other hand are arranged in parallel to each other between the first input and the first output of operational amplifier 76. The connection between switch S75a and capacitor C2a is connected via a switch S77a to ground Vcm, while the connection between capacitor C2a and switch S76a is connected via a switch S78a to ground Vcm.
The second output of the sampling portion 72 is connected to a second input of the LPF portion 75. The second input and output of operational amplifier 76 are connected to the second input of the LPF portion 75 and a second output of the LPF portion 75, respectively, and corresponding components are connected directly and indirectly to the second input and output of operational amplifier 76 as to the first input and output of operational amplifier 76. Corresponding capacitors are named C1b and C2b instead of C1a and C2a, respectively, and corresponding switches are named S75b to S78b instead of S75a to S78a, respectively.
Transconductance element 70 converts two input RF voltage mode signals into RF current mode signals and provides them to the frequency down conversion portion 71. A separate LNA (not shown) can be used in front of transconductance element 70. Alternatively, the transconductance element 70 could be either an integral part of an LNA or of the frequency down-conversion portion 71. However, in any implementation one or more semiconductor devices can be recognized that provide the function of a transconductor.
The local oscillator provides alternating signals LO+ and LO− to the switches of the frequency down conversion portion 71. When the LO+ signal is active, the outputs of the transconductance element 70 are connected to the sampling portion 72 in a direct way, i.e. the first output of the transconductance element 70 is connected to the first path of the sampling portion 72, while the second output of the transconductance element 70 is connected to the second path of the sampling portion 72. When the LO− signal is active, the outputs of the transconductance element 70 are connected to the sampling portion 72 in a cross-coupled way, i.e. the first output of the transconductance element 70 is connected to the second path of the sampling portion 72, while the second output of the transconductance element 70 is connected to the first path of the sampling portion 72. With this operation, the RF current signals output by the transconductance element 70 are frequency down-converted into IF current signals.
In the sampling portion 72, switches S71a, S74a, S71b and S74b are closed during a clock phase φ1, while switches S72a, S73a, S72b and S73b are closed during a clock phase φ2. Clock phases φ1 and φ2 are alternating with each other.
The signal current is thus integrated by the sampling capacitors Csa and Csb during a respective clock phase φ1. The sampling is said to be passive, as no operational amplifier participates in the integration. The sampling capacitors Csa and Csb are then discharged to zero during a charge transfer from the capacitors Csa and Csb to the LPF portion 76 during a respective clock phase φ2. Therefore, an additional reset phase is not needed for discharging the switched capacitors Csa and Csb before the respective next sampling phase. The capacitors Cia and Cib are needed to avoid a shifting of the transfer function zeros due to the non-overlap time of the sampling. In addition, the capacitors Cia and Cib are also used to attenuate RF blockers and interferences.
Alternatively, switches S71a, S72a, S71b and S72b could be closed during a clock phase φ1, while switches S73a, S74a, S73b and S74b are closed during a clock phase φ2. In this case, the charge transfer to the LPF portion 76 takes place during the charging of the capacitors Csa and Csb in a respective clock phase φ1, while clock phase φ2 is a pure discharging phase.
Parallel samplers 74 can be used in order to reduce the sampling clock frequency or to build an analog FIR (finite impulse response) filter sampling stage.
The LPF portion 75 then performs a low-pass filtering on the received current samples. To this end, switches S75a, S76a, S75b and S76b are closed in the respective clock phase φ1, while switches S77a, S78a, S77b and S78b are closed in the respective clock phase φ2.
The power consumption of operational amplifier 76 of the LPF portion 75 can be reduced by a modification as presented in FIG. 8.
The circuit of FIG. 8 comprises exactly the same components as the circuit of FIG. 7, except that the capacitors C2a and C2b and the switches S75a to S78a and S75b to S78b are removed. Moreover, switch S73a in the first depicted path of the sampling portion 72 is no longer connected to ground Vcm, but instead to the first output of operational amplifier 76. The connection between switch S73a and the capacitor Csa is connected within the sampling portion 72 via a switch S81a to the connection between switch S74a and the capacitor Csa. A corresponding arrangement is introduced between the second output of operational amplifier 76 and the second depicted path in the sampling portion 72, including switch S81b. The outputs of the operational amplifier 76 are moreover connected in the same manner in parallel to the first and the second paths in any possible further sampler 74.
The sampling operation is similar to the sampling operation in the circuit of FIG. 7. In this case, however, capacitors Csa and Csb are charged during a respective clock phase φ1, connected to operational amplifier 76 during a respective clock phase φ2, and discharged during a respective additional reset clock phase φr by closing switches S81a and S81b. 
Compared to the circuit of FIG. 7, a lower power consumption is achieved, since the workload of operational amplifier 76 is relaxed in the charge transfer clock phase φ2 due to the modified switching topology. The main drawback of this circuit is, however, that the additional reset clock phase φr is needed for discharging the switched capacitors Csa and Csb before the respective next sampling. Due to the additional reset clock phase φr, parallel samplers 74 are required in addition to sampler 73.
In a passive current mode sampling, the current consumption of the operational amplifier of an LPF portion could also be reduced by means of a decimation circuit as presented by S. Lindfors in: “CMOS Baseband Integrated Circuit Techniques for Radio Receivers”, doctoral thesis, Helsinki University of Technology, July 2000. In that topology, the sampling frequency of a switched capacitor connected to the operational amplifier can be smaller than the input sampling frequency of the current mode sampling, resulting in lower bandwidth requirements for the operational amplifier.
A serious drawback of a passive current mode sampling in general, however, results from the common use of transistors as switches.
Transistors in modern semiconductor processes have a low output impedance, such that also the employed transconductance elements in the presented circuits have a low output impedance. This low output impedance causes a leakage of the transfer function zeros and thus degrades the advantageous anti-alias filter properties of the current mode sampling. The problem becomes severe, when the passive current mode sampling is implemented using components available in digital deep-sub micron CMOS processes, where the output impedance of the realized components is inherently low.
Another serious drawback resulting from the low output impedance is poor linearity for the third order intercept point, IIP3. As the integrated voltage in the sampling capacitors, and thus the voltage at the output of the mixer and in some cases also of the transconductance element, is a function of the input signal, a signal dependent distortion is introduced due to channel modulation effects in the mixing transistors of the frequency down-conversion portion.
A known circuit topology that circumvents the problem resulting from the low output impedance of the transconductance element and from the non-linearity of the transistors mixing the RF signal is shown in FIG. 9, which enables an active current mode sampling instead of a passive current mode sampling.
The circuit of FIG. 9 comprises as well a transconductance element 90 for converting RF voltage mode signals into RF current mode signals and a frequency down-conversion portion 91 for frequency down-converting the RF current signals into IF current signals, as described above with reference to FIG. 7. In addition, the circuit of FIG. 9 comprises a sampling and LPF portion 92 and a following switched-capacitor (SC) block 94 realizing a part of an ADC or an SC-filter.
The sampling and LPF portion 92 comprises an operational amplifier 93. The first output of the frequency down-conversion portion 91 is connected via a first input of the sampling and LPF portion 92 to a first input of operational amplifier 93, and a first output of operational amplifier 93 is connected to a first output of the sampling and LPF portion 92. A capacitor C1a on the one hand and a series connection of a switch S91a, a capacitor C2a and a switch S92a on the other hand are arranged in parallel to each other between the first input and the first output of operational amplifier 93. The connection between switch S91a and capacitor C2a is connected via a switch S93a to ground Vcm, while the connection between capacitor C2a and switch S92a is connected via a switch S94a to ground Vcm.
The second output of the frequency down-conversion portion 91 is connected to a second input of the sampling and LPF portion 92. A second input and output of operational amplifier 93 are connected to the second input of the sampling and LPF portion 92 and a second output of the sampling and LPF portion 92, respectively, and corresponding components are connected directly and indirectly to the second input and output of operational amplifier 93 as to the first input and output of operational amplifier 93. Corresponding capacitors are named C1b and C2b instead of C1a and C2a, respectively, and corresponding switches are named S91b to S94b instead of S91a to S94a, respectively.
The components of the sampling and LPF portion 92 form an active switched-capacitor integrator.
The first output of the sampling and LPF portion 92 is connected within the SC block 94 via a switch S95a, a sampling capacitor C4a and a switch S96a to a first input of an operational amplifier 95. In addition, the connection between switch S95a and capacitor C4a is connected via a switch S97a to ground Vcm, while the connection between capacitor C4a and switch S96a is connected via a switch S98a to ground Vcm. The second output of the of the sampling and LPF portion 92 is connected within the SC block 94 in exactly the same manner to a second input of operational amplifier 95. A corresponding capacitor is named C4b instead of C4a, and corresponding switches are named S95b to S98b instead of S95a to S98a, respectively.
A respective capacitor C3a, C3b is arranged between the first input and a first output of the operational amplifier 95 and between the second input and a second output of the operational amplifier 95. Further elements may be connected in parallel to the respective capacitor C3a, C3b for realizing the desired functions.
In the sampling and LPF portion 92, switches S91a, S92a, S91b and S92b are closed during a clock phase φ1, while switches S93a, S94a, S93b and S94b are closed during a clock phase φ2. Capacitors C2a and C2b are therefore charged during a respective clock phase φ1 and discharged to zero during a respective clock phase φ2, the latter constituting a dedicated reset clock phase. Clock phases φ1 and φ2 are alternating with each other.
The current mode signals provided by the frequency down-conversion portion 92 are thus integrated by the active switched-capacitor integrator of the sampling and LPF portion 92, which provides a virtual short circuit at the sampler input. The switched-capacitor integrator does not allow the output voltage of the frequency down conversion portion 91 and, in some cases, of the transconductance element 90 to vary, as the signals are in a current mode. Therefore, a leakage of the transfer function zeros due to the small output impedance is eliminated and better quality anti-alias filtering properties are obtained. In addition, as the voltage swing is practically negligible, a better linearity (IIP3) is obtained. With the shown switched-capacitor integrator, or alternatively with another higher order filter, also the RF blockers are attenuated.
In the SC block 94, switches S95a, S96a, S95b and S96b are closed during a clock phase φ1, while switches S97a, S98a, S97b and S98b are closed during a clock phase φ2. Sampling capacitors C4a and C4b are therefore charged during the respective clock phase φ1 and discharged to zero during the respective clock phase φ2. The sampled signal is then further processed as desired by the operational amplifier 95.
It is a disadvantage of the circuit of FIG. 9 that it involves a high power consumption as, for example, power is wasted during the reset clock phase φ2. The power consumption is heavily dependent on the switching frequency and on the capacitance values of capacitors C2a and C2b on the one hand and C4a and C4b on the other hand. The problem is that while it is desirable to have a low switching frequency for achieving a low power consumption, it is desirable to have a high switching frequency for a wide bandwidth of the transfer function zeros relative to the signal bandwidth.
Due to the high power consumption, an active current mode sampling is currently only used for sampling an IF input signal, as described in the above mentioned document “A Charge Sampling Mixer With Embedded Filter Function for Wireless Applications”.